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Integrated Circuit Systems, Inc.
ICS952624
Programmable Timing Control HubTM for Next Gen P4TM processor
Recommended Application: CK409 48-pin part Output Features: * 2 - 0.7V current-mode differential CPU pairs * 1 - 0.7V current-mode differential CPU pairs for ITP * 1 - 0.7V current-mode differential SRC pair * 9 - PCI (33MHz) * 1 - USB, 48MHz * 1 - DOT, 48MHz * 2 - REF, 14.318MHz * 3 - 3V66, 66.66MHz * 1 - 3V66/VCH, selectable 48MHz or 66MHz Features/Benefits: * Supports tight ppm accuracy clocks for Serial-ATA * Supports spread spectrum modulation, 0 to -0.5% down spread and +/- 0.25% center spread * * * Supports CPU clks up to 400MHz in test mode Uses external 14.318MHz crystal Supports undriven differential CPU, SRC pair in PD# and CPU_STOP# for power management.
Key Specifications: * CPU/SRC outputs cycle-cycle jitter < 125ps * 3V66 outputs cycle-cycle jitter < 250ps * * * PCI outputs cycle-cycle jitter < 250ps CPU outputs skew: < 100ps +/- 300ppm frequency accuracy on CPU & SRC clocks
Pin Configuration
Functionality
USB/ FS2 CPU SRC 3V66 PCI REF DOT B6b5 FS_A FS_B MHz MHz MHz MHz MHz MHz 0 0 100.00 100/200 66.66 33.33 14.318 48.00 0 1 200.00 100/200 66.66 33.33 14.318 48.00 0 1 0 133.33 100/200 66.66 33.33 14.318 48.00 1 1 166.66 100/200 66.66 33.33 14.318 48.00 0 0 200.00 100/200 66.66 33.33 14.318 48.00 0 1 400.00 100/200 66.66 33.33 14.318 48.00 1 1 0 266.66 100/200 66.66 33.33 14.318 48.00 1 1 333.33 100/200 66.66 33.33 14.318 48.00
*FS_A/REF1 *FS_B/REF0 VDDREF X1 X2 GND PCICLK_F0 PCICLK_F1 PCICLK_F2 VDDPCI GND PCICLK0 PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PD# 48MHz_DOT 48MHz_USB GND VDD48
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDDA GND IREF CPUCLKT_ITP CPUCLKC_ITP GND CPUCLKT1 CPUCLKC1 VDDCPU CPUCLKT0 CPUCLKC0 GND SRCCLKT SRCCLKC VDD VttPWR_GD# SDATA SCLK 3V66_0 3V66_1 GND VDD3V66 3V66_2 3V66_3/VCH
*120K pull-up 48-pin SSOP
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ICS952624
Integrated Circuit Systems, Inc.
ICS952624
Pin Description
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN NAME FS_A/REF1 FS_B/REF0 VDDREF X1 X2 GND PCICLK_F0 PCICLK_F1 PCICLK_F2 VDDPCI GND PCICLK0 PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PD# 48MHz_DOT 48MHz_USB GND VDD48 PIN TYPE I/O I/O PWR IN OUT PWR OUT OUT OUT PWR PWR OUT OUT OUT OUT PWR PWR OUT OUT IN OUT OUT PWR PWR DESCRIPTION FS_A latched input for frequency select Reference output, 14.318Hz FS_B latched input for frequency select Reference output, 14.318Hz Ref, XTAL power supply, nominal 3.3V Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Ground pin. Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. PCI clock output. PCI clock output. Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 1.8ms. 48.008MHz Dot clock output 48.008MHz USB clock output Ground pin. Power for 48MHz output buffers and fixed PLL core.
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Integrated Circuit Systems, Inc.
ICS952624
Pin Description (Continued)
PIN # 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PIN NAME 3V66_3/VCH 3V66_2 VDD3V66 GND 3V66_1 3V66_0 SCLK SDATA VttPWR_GD# VDD SRCCLKC SRCCLKT GND CPUCLKC0 CPUCLKT0 VDDCPU CPUCLKC1 CPUCLKT1 GND CPUCLKC_ITP CPUCLKT_ITP IREF GND VDDA PIN TYPE OUT OUT PWR PWR OUT OUT IN I/O IN OUT OUT OUT PWR OUT OUT PWR OUT OUT PWR OUT OUT OUT PWR PWR DESCRIPTION 3.3V 66.66MHz clock output VCH: 48MHz VCH clock output 3.3V 66.66MHz clock output Power pin for the 3V66 clocks. Ground pin. 3.3V 66.66MHz clock output 3.3V 66.66MHz clock output Clock pin of I2C circuitry 5V tolerant Data pin for I2C circuitry 5V tolerant This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active low input. Power supply, nominal 3.3V Complementary clock of differential pair for S-ATA support. +/- 300ppm accuracy required. True clock of differential pair for S-ATA support. +/- 300ppm accuracy required. Ground pin. "Complimentary" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal "Complimentary" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Ground pin. "Complementary" clocks of differential pair CPU outputs for ITP.. These are current mode outputs. External resistors are required for voltage bias. "True" clocks of differential pair CPU outputs for ITP. These are current mode outputs. External resistors are required for voltage bias. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin. 3.3V power for the PLL core.
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ICS952624
General Description
ICS952624 is a programmable 48 pin clock chip following Intel CK409 Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS952624 is driven with a 14.318MHz crystal. It generates CPU outputs up to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support.
Block Diagram
PLL2 Frequency Dividers 48MHz, USB, DOT, VCH
X1 X2
XTAL
REF (1:0) CPUCLKT (1:0) CPUCLKC (1:0) SRCCLKT0 Programmable Spread PLL1 Programmable Frequency Dividers STOP Logic SRCCLKC0 3V66(3:0) PCICLK (8:0)
SCLK SDATA VTTPWRGD# PD# FS_A FS_B Control Logic
CPUCLKT_ITP CPUCLKC_ITP I REF
Power Groups
Pin Number VDD GND 3 6 27 28 10,16 11,17 34 37 48 47 24 23 -47 40 43 Description Xtal, Ref 3V66 [0:3] PCICLK outputs SRCCLK outputs Master clock, CPU Analog 48MHz, Fix Digital, Fix Analog IREF CPUCLK clocks
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ICS952624
Absolute Max
Symbol VDD_A VDD_In Ts Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min -0.5 -65 0 Max VDD + 0.5V VDD + 0.5V 150 70 115 Units V V C C C V
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL VIH VIL IIH IIL1 Input Low Current IIL2 Operating Supply Current Powerdown Current Input Frequency3 Pin Inductance1 Input Capacitance1 IDD3.3OP IDD3.3PD Fi Lpin CIN COUT CINX CONDITIONS 3.3V +/-5% 3.3V +/-5% VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors Full Active, CL = Full load; all diff pairs driven all differential pairs tri-stated VDD = 3.3 V MIN 2 VSS 0.3 -5 -5 -200 260 31 0.300 14.31818 350 35 12 7 5 6 5 TYP MAX VDD + 0.3 0.8 5 UNITS NOTES V V uA uA uA mA mA mA MHz nH pF pF pF ms kHz us ns ns
Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or deTSTAB 1.8 Clk Stabilization1,2 assertion of PD# to 1st clock. Triangular Modulation 30 33 Modulation Frequency CPU output enable after Tdrive_PD# 300 PD# de-assertion Tfall_Pd# PD# fall time of 5 Trise_Pd# PD# rise time of 5 1 Guaranteed by design, not 100% tested in production. 2 See timing diagrams for timing requirements. 3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
3 1 1 1 1 1,2 1 1 1 2
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ICS952624
Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3V +/-5%; CL =2pF PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL Zo
1
CONDITIONS VO = Vx Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 200MHz nominal 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V
MIN 3000 660 -150 -300 250
TYP
MAX
UNITS
NOTES 1 1
VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm
749 3 756 -7 350 12
850 mV 150 1150 550 140 mV mV mV ppm ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps
1 1 1 1 1 1,2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1 1 1 1 1 1 1
Average period
Tperiod
Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle
Tabsmin tr tf d-tr d-tf dt3
-300 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 4.8735 5.8732 7.3728 9.8720 175 175
300 5.0015 5.0266 6.000 6.0018 6.0320 7.500 7.5023 5.4000 10.000 10.0030 10.0533 5.000
279 280 30 30
700 700 125 125
Measurement from differential 45 50.9 55 % wavefrom tsk3 VT = 50% Skew 8 100 ps Measurement from differential tjcyc-cyc 40 125 ps Jitter, Cycle to cycle wavefrom 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz SRC clock outputs run at only 100MHz or 200MHz, specs for 133.33 and 166.66 do not apply to SRC clock pair.
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ICS952624
Electrical Characteristics - 3V66 Mode: 3V66 [3:0]
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Long Accuracy ppm see Tperiod min-max values 66.66MHz output nominal Tperiod Clock period 66.66MHz output spread IOH = -1 mA VOH Output High Voltage VOL IOL = 1 mA Output Low Voltage V OH@MIN = 1.0 V IOH Output High Current VOH@MAX = 3.135 V VOL @MIN = 1.95 V IOL Output Low Current VOL@MAX = 0.4 V Edge Rate Rising edge rate Edge Rate Falling edge rate VOL = 0.4 V, VOH = 2.4 V tr1 Rise Time tf1 VOH = 2.4 V, VOL = 0.4 V Fall Time dt1 VT = 1.5 V Duty Cycle Skew Jitter
1
MIN -300 14.9955 14.9955 2.4 -33
TYP 15
MAX 300 15.0045 15.0799 0.55 -33
30 1 1 0.5 0.5 45 38 4 4 2 2 55 250 250
1.79 1.69 50 80 172
UNITS ppm ns ns V V mA mA mA mA V/ns V/ns ns ns % ps ps
Notes 1,2 2 2
1 1 1 1 1 1 1
tsk1 tjcyc-cyc
VT = 1.5 V VT = 1.5 V 3V66
Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Edge Rate Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL ppm Tperiod VOH VOL IOH IOL
CONDITIONS see Tperiod min-max values 33.33MHz output nominal 33.33MHz output spread IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V VOH@MAX = 3.135 V VOL@MIN = 1.95 V VOL@MAX = 0.4 V Rising edge rate Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 3V66
MIN -300 29.9910 29.9910 2.4 -33
TYP
MAX
UNITS ppm ns ns V V mA mA mA mA V/ns V/ns ns ns % ps ps
Notes 1,2 2 2
300 30 30.0090 30.1598 0.55 -33
30 1 1 0.5 0.5 45 38 4 4 2 2 55 500 250
tr1 tf1 dt1 tsk1 tjcyc-cyc
1.79 1.69 50 95 140
1 1 1 1 1 1 1
Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz
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ICS952624
Electrical Characteristics - 48MHz DOT Clock
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 5-10 pF (unless otherwise specified) PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Edge Rate Rise Time Fall Time Duty Cycle Skew tr1 tf1 dt1 tsk1 SYMBOL ppm Tperiod VOH VOL IOH IOL CONDITIONS see Tperiod min-max values 48.008MHz output nominal IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V VOH@MAX = 3.135 V VOL @MIN = 1.95 V VOL@MAX = 0.4 V Rising edge rate Falling edge rate VOL = 0.4 V, VOH = 2.4 V MIN TYP MAX -200 200 20.8257 20.8340 2.4 0.55 -33 -33 30 38 2 4 2 4 0.5 0.87 1 UNITS ppm ns V V mA mA mA mA V/ns V/ns ns Notes 1,2 2
1 1 1 1 1 1 1
VOH = 2.4 V, VOL = 0.4 V 0.5 0.89 1 ns VT = 1.5 V 45 52.3 55 % VT = 1.5 V 1 ns 125us period jitter Long Term Jitter 0.636 2 ns (8kHz frequency modulation amplitude) 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz
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Integrated Circuit Systems, Inc.
ICS952624
Electrical Characteristics - VCH, 48MHz, 48MHz, USB
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage SYMBOL ppm Tperiod VOH VOL CONDITIONS MIN TYP MAX UNITS Notes 1,2 2
see Tperiod min-max values -200 200 ppm 48.008MHz output nominal 20.8257 20.8340 ns IOH = -1 mA 2.4 V IOL = 1 mA 0.55 V V OH@MIN = 1.0 V -33 mA IOH Output High Current VOH@MAX = 3.135 V -33 mA VOL @MIN = 1.95 V 30 mA IOL Output Low Current VOL@MAX = 0.4 V 38 mA Rising edge rate 1 2 V/ns Edge Rate Edge Rate Falling edge rate 1 2 V/ns VOL = 0.4 V, VOH = 2.4 V tr1 1 1.45 2 ns Rise Time VOH = 2.4 V, VOL = 0.4 V tf1 1 1.37 2 ns Fall Time dt1 VT = 1.5 V Duty Cycle 45 52.5 55 % tsk1 VT = 1.5 V Skew 1 ns 125us period jitter Long Term Jitter 0.626 6 ns (8kHz frequency modulation amplitude) 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz
1 1 1 1 1 1 1
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ICS952624
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Skew Duty Cycle Jitter
1
SYMBOL ppm Tperiod VOH1 VOL1 IOH1 IOL1 tr11 tf11 tsk11 dt11 tjcyc-cyc1
CONDITIONS
MIN
TYP
MAX
UNITS ppm ns V V mA mA ns ns ps % ps
Notes 1
see Tperiod min-max values -300 300 14.318 MHz output nominal 69.8270 69.8550 IOH = -1 mA 2.4 IOL = 1 mA 0.4 V OH@MIN = 1.0 V, V OH@MAX = -29 -23 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 29 27 V VOL = 0.4 V, VOH = 2.4 V 1 1.93 2 VOH = 2.4 V, VOL = 0.4 V 1 1.92 2 VT = 1.5 V 14 500 VT = 1.5 V 45 53.8 55 VT = 1.5 V 400 1000
1 1 1 1 1
Guaranteed by design, not 100% tested in production.
Group to Group Skews at Common Transition Edges
GROUP 3V66 to PCI DOT-USB DOT-VCH SYMBOL S3V66-PCI SDOT_USB SDOT_VCH CONDITIONS 3V66 (4:0) leads 33MHz PCI 180 degrees out of phase in phase MIN 1.50 0.00 0.00 TYP 2 MAX 3.50 1.00 1.00 UNITS ns ns ns
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ICS952624
I2C Table: Read-Back Register Byte 0 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -
Name Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Freq Select 1 Read FSB Back Freq Select 0 Read FSA Back
Type R R R R R
0 1 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED READBACK of CPU(2:0) Frequency
PWD X X X X X X X X
I2C Table: Spreading and Device Behavior Control Register Byte 1 Pin # Name Control Function SRC Free-Running Bit 7 SRC/SRC# Control Bit 6 SRC Output Control RESERVED Bit 5 RESERVED Bit 4 RESERVED Bit 3 RESERVED Bit 2 Bit 1 CPUT1/CPUC1 Output Control Bit 0 CPUT0/CPUC0 Output Enable
Type RW RW R R R R RW RW
FREE-RUN
1 STOPPAB LE Disable Enable RESERVED RESERVED RESERVED RESERVED Disable Enable Disable Enable
0
PWD 0 1 X X X X 1 1
I2C Table: Output Control Register Byte 2 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name SRC_PD# Drive Mode SRC_Stop# Drive Mode RESERVED CPUT1_PD# Drive Mode CPUT0_PD# Drive Mode RESERVED RESERVED RESERVED
Control Function 0: Driven in PD# 0: Driven in PCI_Stop# RESERVED 0:driven in PD# 1: Tri-stated RESERVED RESERVED RESERVED
Type RW RW RW RW -
0 Driven Driven
1 Hi-Z Hi-Z
PWD 0 0 X 0 0 X X X
RESERVED Driven Hi-Z Driven Hi-Z RESERVED RESERVED RESERVED
I2C Table: Output Control Register Byte 3 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name PCI_Stop# RESERVED PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
Control Function PCI_Stop# Control 0:all stoppable PCI are stopped RESERVED RESERVED Output Control Output Control Output Control Output Control Output Control
Type RW RW RW RW RW RW
0 Enable
1 Disable
PWD 1 X X 1 1 1 1 1
RESERVED RESERVED Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable
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ICS952624
I2C Table: Output Control Register Byte 4 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name 48MHz_USB 2x output drive 48MHz_USB RESERVED RESERVED RESERVED PCICLK_F2 PCICLK_F1 PCICLK_F0
Control Function 0=2x drive Output Control RESERVED RESERVED RESERVED Output Control Output Control Output Control
Type RW RW RW RW RW
0 2x drive
1 1xdrive
PWD 1 1 X X X 1 1 1
Disable Enable RESERVED RESERVED RESERVED Disable Enable Disable Enable Disable Enable
I2C Table: Output Control Register Byte 5 Pin # Name Bit 7 DOT_48MHZ Bit 6 CPU_T/C_ITP 3V66_3/VHC Bit 5 Frequency Select Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3V66_3/VHC RESERVED 3V66_2 3V66_1 3V66_0
Control Function Output Control Output Control Output Select Output Control RESERVED Output Control Output Control Output Control
Type RW RW RW RW RW RW RW
0 Disable Disable 3V66 Disable
1 Enable Enable VCH Enable
PWD 1 1 0 1 X 1 1 1
RESERVED Disable Enable Disable Enable Disable Enable
I2C Table: Output Control and Fix Frequecy Register Byte 6 Pin # Name Bit 7 Test Clock Mode Bit 6 RESERVED Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPU *2 Test Clock SRC Frequency Select Spread Spectrum Type Spread Spectrum Mode REF1 REF0
Control Function Test Clock Mode FS_A and FS_B Operation SRC Frequency Select Down/Center Spread Spectrum Enable Output Control Output Control
Type -
0 Disable Normal 100MHz Down Spread OFF Disable Disable
1 Enable Test Mode 200MHz Center Spread ON Enable Enable
PWD 0 0 0 0 0 0 1 1
RW RW
I2C Table: Vendor & Revision ID Register Byte 7 Pin # Name Bit 7 RID3 Bit 6 RID2 Bit 5 RID1 Bit 4 RID0 Bit 3 VID3 Bit 2 VID2 Bit 1 VID1 Bit 0 VID0
Control Function REVISION ID
VENDOR ID
Type R R R R R R R R
0 -
1 -
PWD 0 0 0 0 0 0 0 1
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ICS952624
I2C Table: Byte Count Register Byte 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Control Function Writing to this register will configure how many bytes will be read back, default is 08 = 8 bytes. Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 1 0 0 0
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ICS952624
PD#, Power Down
PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power. When PD# is asserted low all clocks will be driven low before turning off the VCO. In PD# de-assertion all clocks will start without glitches.
PWRDWN# 1 0
CPU Normal Iref * 2 or Float
CPU # Normal Float
SRC Normal Iref * 2 or Float
SRC# Normal Float
3V66 66MHz Low
PCIF/PCI 33MHz Low
USB/DOT 48MHz Low
REF 14.318MHz Low
Note
Notes: 1. Refer to tristate control of CPU and SRC clocks in section 7.7 for tristate timing and operation. 2. Refer to Control Registers in section 16 for CPU_Stop, SRC_Stop and PwrDwn SMBus tristate control addresses.
PD# Assertion
PD# should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be held low on their next high to low transition. All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven. When the drive mode but corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at 2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will the tristated.
PWRDWN# CPU, 133MHz CPU#, 133MHz SRC, 100MHz SRC#, 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF, 14.31818
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PD# De-assertion
The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD# tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of 200mV in less than 300s of PD# deassertion.
Tstable <1.8mS PWRDWN# CPU, 133MHz CPU#, 133MHz SRC, 100MHz SRC# 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF, 14.31818 Tdrive_PwrDwn# <300S, >200mV
3V66_3/VCH Pin Functionality
The 3V66_4/VCH pin can be configured to be a 66.66MHz modulated output or a non-spread 48MHz output. The default is 3V66 clock. The switching is controlled by Byte 5 Bit 5. If it is set to '1' this pin will output the 48MHz VCH clock. The output will go low on the falling edge of 3V66 for a minimum of 7.49ns. Then the output will transition to 48MHz on the next rising edge of DOT_48 clock.
3V66
3V66_4/VCH
DOT_48 7.49nS min
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ICS952624
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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ICS952624
N
c
SYMBOL
L
E1 INDEX AREA
E
12 h x 45 D
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
VARIATIONS N 48
10-0034
D mm. MIN 15.75 MAX 16.00 MIN .620
D (inch) MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
Ordering Information
ICS952624yFT
Example:
ICS XXXXXX y F - T
Designation for tape and reel packaging Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0768B--08/06/03
17

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